Integrated circuit

ABSTRACT

An integrated circuit that enables a reduction in chip size and test time. This integrated circuit comprises an internal circuit; an external memory control circuit for inputting read data from an LSI tester by the use of a read command and for outputting write data to the LSI tester by the use of a write command; a test RAM including a read data storage section for storing the read data inputted from the LSI tester at a low speed and a write data storage section for storing the write data outputted from the control circuit; a test circuit for interpreting the read command and the write command issued by the external memory control circuit, for supplying, at the time of determining that the read data must be inputted to the external memory control circuit, the read data from the test RAM to the external memory control circuit at a high speed, and for supplying, at the time of determining that the write data is outputted from the external memory control circuit, the write data outputted from the external memory control circuit to the test RAM at a high speed; and a test circuit for outputting the write data stored in the test RAM to the LSI tester at a low speed.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefits of priority fromthe prior Japanese Patent Application No. 2006-223281, filed on Aug. 18,2006, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

This invention relates to an integrated circuit and, more particularly,to an integrated circuit capable of verifying the operation speed of acircuit.

(2) Description of the Related Art

In recent years there have been many cases where an ordinarysemiconductor integrated circuit to which a high-speed random accessmemory (RAM) is externally connected is used. The high-speed RAM is aRAM in which a data input-output rate is higher than the rate of anordinary semiconductor tester, or a RAM the operation speed of which isso high that data which is outputted from the semiconductor integratedcircuit and which is synchronized with a clock cannot be inputted from asemiconductor tester because of process variation.

There are various known methods for testing such a high-speed RAM (see,for example, Japanese Patent Laid-Open Publication No. 2003-4809).

FIG. 27 is a block diagram showing a conventional system for testing asemiconductor integrated circuit.

A semiconductor integrated circuit 90 includes an internal circuit 91 tobe measured, storage circuits 92 and 93 connected to input and outputsides, respectively, of the internal circuit 91, a buffer 94 forinputting a low-speed test pattern, a buffer 95 for outputting thelow-speed test pattern, input terminals 96 of large-scale integration(LSI) where various signals are inputted from the outside, outputterminals 97 where expected output values are outputted to the outside,and an oscillation circuit 98, such as a phase locked loop (PLL), forgenerating a high-speed clock signal by multiplying a low-speed clocksignal.

In FIG. 27, the storage circuits 92 and 93 store data every clock duringa test period by the operation of the oscillation circuit 98.Accordingly, the maximum number of test patterns from the start tostopping of the operation of the oscillation circuit 98 is limited bythe capacity of the storage circuits 92 and 93. The number of testpatterns is large, so the process “input data to storage circuit lock uposcillation circuit perform high-speed test output data from storagecircuit” must be repeated more than once.

FIG. 28 shows waveforms indicative of the operation of the conventionalsystem.

When a test mode is data input, the storage circuit 92 is written at alow speed. When the test mode is lockup, the oscillation circuit 98 ismade to operate, and is waited for to stabilize. When the test mode is ahigh-speed test, data stored in the storage circuit 92 is inputted and ahigh-speed test is performed with the storage circuit 93 as adestination to which data is outputted. When the test mode is datainput-output, data to be used in the next test is written to the storagecircuit 92 at a low speed and data stored in the storage circuit 93 isoutputted to the outside at a low speed.

With such a test system, however, the following problems arise. Toperform a troublesome test such as a test in which an animation isencoded or decoded, it is necessary to input about several megabytes ofdata to the storage circuit 92 and to output about several megabytes ofdata from the storage circuit 93. In this case, RAMs having very largecapacity must be used as the storage circuits 92 and 93. Alternatively,a test must be performed plural times by using RAMs each having acapacity of several kilobytes to several tens of kilobytes. If a test isperformed plural times, the state of the internal circuit 91 must beheld while the oscillation circuit 98 is at a stop. In addition, thestorage circuits 92 and 93 also store meaningless data, that is to say,write data which exists at the time of write enable not being asserted,read data which exists at the time of data not being needed by theinternal circuit 91, and the like. As a result, storage capacity wastedincreases and time is wasted in inputting unnecessary data andoutputting and determining meaningless data. Therefore, the size of anintegrated circuit chip increases and test time lengthens.

SUMMARY OF THE INVENTION

The present invention was made under the background circumstancesdescribed above. An object of the present invention is to provide anintegrated circuit that enables a reduction in chip size and test time.

In order to achieve the above object, an integrated circuit capable ofverifying the operation speed of a circuit is provided. This integratedcircuit comprises an internal circuit to be tested, a control circuitlocated between the internal circuit and an external device forinputting read data inputted to the internal circuit from the externaldevice by the use of a read command and for outputting write dataoutputted from the internal circuit to the external device by the use ofa write command, a test storage section including a read data storagesection for storing the read data inputted at a low speed and a writedata storage section for storing the write data outputted from thecontrol circuit, a command interpretation circuit for interpreting theread command and the write command issued from the control circuit, forsupplying, at the time of determining that the read data must beinputted to the control circuit, the read data from the test storagesection to the control circuit at a high speed, and for supplying, atthe time of determining that the write data is outputted from thecontrol circuit, the write data outputted from the control circuit tothe test storage section at a high speed, an input circuit for inputtingthe read data inputted from the external device to the test storagesection at a low speed, and an output circuit for outputting the writedata supplied to the test storage section to the external device at alow speed.

The above and other objects, features and advantages of the presentinvention will become apparent from the following description when takenin conjunction with the accompanying drawings which illustrate preferredembodiments of the present invention by way of example.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a system according to a firstembodiment of the present invention.

FIG. 2 shows waveforms indicative of the operation of an integratedcircuit according to the first embodiment of the present invention.

FIG. 3 shows another example of the operation of the integrated circuitaccording to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a system according to a secondembodiment of the present invention.

FIG. 5 is block diagram showing a system according to a third embodimentof the present invention.

FIG. 6 is a block diagram showing an integrated circuit according to afourth embodiment of the present invention.

FIG. 7 shows a low-speed data input circuit.

FIG. 8 shows a low-speed data output circuit.

FIG. 9 shows waveforms indicative of the operation of the integratedcircuit according to the fourth embodiment of the present invention.

FIG. 10 shows waveforms indicative of the operation of the integratedcircuit according to the fourth embodiment of the present invention.

FIG. 11 is block diagram showing a system according to a fifthembodiment of the present invention.

FIG. 12 is a circuit diagram showing a low-speed data output circuitincluded in an integrated circuit according to the fifth embodiment ofthe present invention.

FIG. 13 shows waveforms indicative of the operation of an integratedcircuit according to a sixth embodiment of the present invention.

FIG. 14 shows waveforms indicative of the operation of the integratedcircuit according to the sixth embodiment of the present invention.

FIG. 15 is block diagram showing a system according to a seventhembodiment of the present invention.

FIG. 16 shows a low-speed data input circuit included in an integratedcircuit according to the seventh embodiment of the present invention.

FIG. 17 shows a low-speed data output circuit included in the integratedcircuit according to the seventh embodiment of the present invention.

FIG. 18 shows waveforms indicative of the operation of the integratedcircuit according to the seventh embodiment of the present invention.

FIG. 19 is block diagram showing a system according to an eighthembodiment of the present invention.

FIG. 20 shows a data input circuit included in an integrated circuitaccording to the eighth embodiment of the present invention.

FIG. 21 shows a data output circuit included in the integrated circuitaccording to the eighth embodiment of the present invention.

FIG. 22 shows waveforms indicative of the operation of an integratedcircuit according to a ninth embodiment of the present invention.

FIG. 23 is block diagram showing a system according to a tenthembodiment of the present invention.

FIG. 24 shows waveforms indicative of the operation of an integratedcircuit according to the tenth embodiment of the present invention.

FIG. 25 is block diagram showing a system according to an eleventhembodiment of the present invention.

FIG. 26 shows waveforms indicative of the operation of an integratedcircuit according to the eleventh embodiment of the present invention.

FIG. 27 is a block diagram showing a conventional system for testing asemiconductor integrated circuit.

FIG. 28 shows waveforms indicative of the operation of the conventionalsystem.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will now be described in detailwith reference to the drawings.

FIG. 1 is a block diagram showing a system according to a firstembodiment of the present invention.

A system according to a first embodiment of the present inventioncomprises an integrated circuit 100 and an LSI tester 200.

The LSI tester 200 is used for testing the operation of the integratedcircuit 100 and inputs various test signals to a plurality of terminalsof the integrated circuit 100.

The integrated circuit 100 includes an internal circuit 10, an externalmemory control circuit 11, an oscillation circuit 12, a test RAM 13,test circuits 14 and 15, an I/O 16, a test selector 17, and a testsignal input section 18.

The internal circuit 10 is a circuit to be measured.

The external memory control circuit 11 outputs a command to the testcircuit 14 and exchanges data with the test RAM 13.

Furthermore, the external memory control circuit 11 exchanges data (readdata and write data) and the like with the LSI tester 200 via the I/O 16by using an address/command (read command or write command). Theexternal memory control circuit 11 may be integrated with the internalcircuit 10.

The oscillation circuit 12 multiplies a low-speed clock inputted fromthe test signal input section 18 and generates an I/O clock (high-speedclock) the frequency of which is n times (five times, for example) thefrequency of the low-speed clock. The oscillation circuit 12 suppliesthe I/O clock to the internal circuit 10, the external memory controlcircuit 11, and the test circuit 14.

The operation/stop of a clock generation circuit in the oscillationcircuit 12 is controlled by a clock enable signal.

In this case, a “low-speed clock” is a clock slower than one of (1) theminimum cycle of a tester clock usually used and (2) a minimum cycle inwhich a test can stably be performed with variations in signal delay inthe integrated circuit caused by processes and variations intemperature/power supply voltage taken into consideration that is thelonger. A “high-speed clock” is a clock faster than one of (1) theminimum cycle of a tester clock usually used and (2) a minimum cycle inwhich a test can stably be performed with variations in signal delay inthe integrated circuit caused by processes and variations intemperature/power supply voltage taken into consideration that is thelonger.

The test RAM 13 can be accessed simultaneously by the test circuits 14and 15. In the test RAM 13, sections for storing the read data andsections for storing the write data are separated. The sections forstoring the read data and the sections for storing the write data may bephysically separated or the addresses of the sections for storing theread data and the addresses of the sections for storing the write datamay be separated.

To “read” means that not the test RAM 13 but the external memory controlcircuit 11 reads. To “write” means that not the test RAM 13 but theexternal memory control circuit 11 writes. If the LSI tester 200transfers data N times in one clock, bit width which the test RAM 13 canhandle may be set to (number of terminals to which the LSI tester 200 isconnected ×N).

The test circuit 14 interprets a command outputted from the externalmemory control circuit 11 and controls timing with which the externalmemory control circuit 11 needs effective data and with which dataoutputted from the external memory control circuit 11 becomes effective.Only when data is effective, the read data is supplied from the test RAM13 to the external memory control circuit 11. In addition, the writedata is supplied from the external memory control circuit 11 to the testRAM 13.

The test circuit 14 operates by the I/O clock, so the read data and thewrite data are supplied at high speeds.

Data by which the external memory control circuit 11 effectivelyoperates is data read out from an external memory or data written to theexternal memory. There is no special limit to noneffective data.Noneffective data is, for example, data which exists when the externalmemory is not read or written by the external memory control circuit 11.

The test circuit 15 designates an address of the test RAM 13 inaccordance-with a control signal inputted, writes the read data to thetest RAM 13 at a low speed, and reads out the write data from the testRAM 13 at a low speed.

The test circuit 15 also supplies a select signal, a write/readidentification signal, and the like to the test RAM 13.

In addition, the test circuit 15 outputs WAIT (WAIT signal) to theexternal memory control circuit 11. The WAIT will be described later.The test circuit 15 only generates the WAIT by decoding and does notcontrol the WAIT.

The I/O 16 includes a plurality of input-output buffers (twoinput-output buffers in this example) and an address/command outputbuffer for the external memory control circuit 11 and functions as aninterface between the LSI tester 200 and the integrated circuit 100. TheI/O 16 exchanges low-speed data read or written at a low speed andhigh-speed data read or written at a high speed with the LSI tester 200.

When the operation of the integrated circuit 100 is tested, the LSItester 200 is connected to the I/O 16. However, after the operation ofthe integrated circuit 100 is tested, an external RAM, such as asynchronous DRAM (SDRAM), is connected to the I/O 16 and high-speed datais exchanged between the I/O 16 and the external RAM.

The test selector 17 includes selectors 171 and 172 for performingswitching to connect the I/O 16 to the external memory control circuit11 or the test RAM 13 and a selector 173 for performing switching toconnect the external memory control circuit 11 to the test RAM 13 or theI/O 16.

A test signal is inputted from the LSI tester 200 to the test signalinput section 18. The test signal input section 18 has a plurality ofinput terminals. To be concrete, the test signal input section 18 has aninput terminal 181 for inputting a reset signal to the internal circuit10, the external memory control circuit 11, and the test circuit 15, aninput terminal 182 for inputting the control signal, an input terminal183 for inputting the low-speed clock, and an input terminal 184 forinputting the clock enable signal.

The LSI tester 200 is connected to the integrated circuit 100 via theI/O 16. When the LSI tester 200 receives an address/command from theexternal memory control circuit 11, the LSI tester 200 exchanges datawith the integrated circuit 100.

The control signal inputted to the test signal input section 18 isgenerated by a simulation performed at the time of generating a testpattern. The LSI tester 200 supplies the control signal generated by thesimulation to the integrated circuit 100. When the simulation isperformed at the time of generating the test pattern, the control signalis generated by a control signal generation simulation model connectedto the integrated circuit 100 via the I/O 16.

When the simulation is performed, it is possible to monitor a signal ina simulation model of the integrated circuit 100 without checking asignal. The control signal generation simulation model has the functionof monitoring the amount of data in a simulation model of the internalcircuit 10 and a simulation model of the test RAM 13. When the testsignal is generated, the control signal generation simulation modelmonitors the amount of data to be read by a read command issued next bya simulation model of the external memory control circuit 11, the amountof data to be written by a write command issued next by the simulationmodel of the external memory control circuit 11, and the amount of readdata and write data stored in the simulation model of the test RAM 13and embeds WAIT/no WAIT in the control signal which is the test signal.The simulation is performed so that it will match the internal operationof the integrated circuit 100. Therefore, even if the control signalgenerated by the simulation is inputted to the integrated circuit 100 onthe basis of time instead of monitoring the operation of the integratedcircuit 100, there arises no problem.

FIG. 2 shows waveforms indicative of the operation of the integratedcircuit according to the first embodiment of the present invention.

In FIG. 2, “read” indicates a read command issued by the external memorycontrol circuit 11 and “write” indicates a write command issued by theexternal memory control circuit 11. “data” indicates read data (R00, forexample) inputted from the LSI tester 200 to the test RAM 13 and writedata (W00, for example) outputted from the test RAM 13 to the LSI tester200. A burst transfer of data which is read out from or written to thetest RAM 13 is performed. Burst length is a multiple of 4. “amount ofread data in test RAM” indicates the amount of read data which is notread out by the test circuit 14 after the test RAM 13 is written at alow speed by the LSI tester 200, and “amount of write data in test RAM”indicates the amount of write data which is not outputted to the I/O 16(external terminal) after the test RAM 13 is written by the test circuit14.

When the oscillation circuit 12 operates, a clock stabilizes, and theinternal circuit 10 begins to operate time A), the LSI tester 200 beginsto write read data to the test RAM 13 at a low speed. That is to say,the LSI tester 200 inputs the read data to the I/O 16 and sends acontrol signal to the test circuit 15 and the test circuit 15 sends anaddress to the test RAM 13. When the LSI tester 200 writes four piecesof read data which are read out once to the test RAM 13 (time B), thereis yet free capacity in the test RAM 13. Accordingly, the LSI tester 200continues to write the read data to the test RAM 13 at a low speed. Whenthe external memory control circuit 11 issues a read command to the testcircuit 14 (time C), the test circuit 14 reads out the four pieces ofread data from the test RAM 13 at a high speed and supplies the fourpieces of read data to the external memory control circuit 11. Afterthat, the external memory control circuit 11 writes write data to thetest RAM 13 at a high speed. When the external memory control circuit 11issues a write command to the test circuit 14, the test circuit 14 readsout the write data from the test RAM 13 to the LSI tester 200 at a lowspeed (time D). All the write data written to the test RAM 13 is readout, so read data is written to the test RAM 13 at a low speed (time E).A control signal (not shown) shows in advance that eight pieces of readdata are to be read out by the next read command issued by the externalmemory control circuit 11. However, only four pieces of read data arestored now in the test RAM 13. Therefore, WAIT is outputted from thetest circuit 15 to the external memory control circuit 11 (time F). Whenthe read data to be read out by the next read command issued by theexternal memory control circuit 11 is all stored in the test RAM 13,WAIT is released and the external memory control circuit 11 issues theread command (time G).

FIG. 3 shows another example of the operation of the integrated circuitaccording to the first embodiment of the present invention.

Compared with the above example, reading out write data (W00 throughW07) from the test RAM 13 is delayed in FIG. 3. As a result, there is noneed to use WAIT.

As has been described above, with the integrated circuit 100 accordingto the first embodiment of the present invention the test circuit 14interprets a command issued by the external memory control circuit 11and transfers only necessary data between the test RAM 13 and theexternal memory control circuit 11. As a result, test time cansignificantly be reduced. Moreover, there is no need to read uselessdata. Therefore, the size of the test RAM 13 can be reduced and the sizeof the integrated circuit 100 can be reduced.

A system according to a second embodiment of the present invention willnow be described.

The differences between the systems according to the first and secondembodiments of the present invention will mainly be described anddescriptions of the same matters will be omitted.

FIG. 4 is a block diagram showing the system according to the secondembodiment of the present invention.

An integrated circuit 100 a according to the second embodiment of thepresent invention differs from the integrated circuit 100 according tothe first embodiment of the present invention in that low-speed datainput-output terminals and high-speed data input-output terminals areseparated. The integrated circuit 100 a includes a test selector 17 a inplace of the test selector 17 and includes an I/O 19 and an inputsection 20.

The test selector 17 a does not include selectors 171 and 172 butincludes a plurality of selectors (selectors 174 and 175, in thisexample) for performing switching between the outputting of low-speedwrite data from an internal circuit 10 and the outputting of low-speedwrite data from a test RAM 13.

The I/O 19 includes a plurality of input-output buffers to whichlow-speed data is inputted bit by bit. The number of the input-outputbuffers which determines the bit width of the I/O 19 may be larger thanthe bit width of data inputted to the test RAM 13.

An I/O 16 included in the integrated circuit 100 a according to thesecond embodiment of the present invention mainly performs high-speeddata input-output.

The input section 20 includes input terminals for inputting selectorsignals for switching a selector 173 and the selectors 174 and 175.

The same effect that is obtained by the system according to the firstembodiment of the present invention can be achieved by the systemaccording to the second embodiment of the present invention.

With the system according to the second embodiment of the presentinvention there is no need to use the selectors 171 and 172. Therefore,timing adjustment can easily be performed in the I/O 16.

A system according to a third embodiment of the present invention willnow be described.

The differences between the systems according to the second and thirdembodiments of the present invention will mainly be described anddescriptions of the same matters will be omitted.

FIG. 5 is block diagram showing the system according to the thirdembodiment of the present invention.

An integrated circuit 100 b according to the third embodiment of thepresent invention differs from the integrated circuit 100 a according tothe second embodiment of the present invention in that it includes anI/O 19 a in which terminals for inputting read data and terminals foroutputting write data are separated.

The same effect that is obtained by the system according to the secondembodiment of the present invention can be achieved by the systemaccording to the third embodiment of the present invention. In addition,with the system according to the third embodiment of the presentinvention the input terminals and the output terminals are separated. Asa result, band width for low-speed data input-output can be increasedand test time can be reduced. Furthermore, when data at a terminal towhich a signal is not frequently inputted at test time is not effective,the terminal can also be used for inputting read data to a test RAM 13.When data at a terminal from which a signal is not frequently outputtedat the test time is not effective, the terminal can also be used foroutputting write data from the test RAM 13. By doing so, a test patterncan be made smaller.

A system according to a fourth embodiment of the present invention willnow be described.

The differences between the systems according to the third and fourthembodiments of the present invention will mainly be described anddescriptions of the same matters will be omitted.

FIG. 6 is a block diagram showing an integrated circuit according to thefourth embodiment of the present invention.

An integrated circuit 100 c according to the fourth embodiment of thepresent invention differs from the integrated circuit 100 b according tothe third embodiment of the present invention in that the bit width ofinput terminals and output terminals included in an I/O 19 b is smallerthan bit width which an LSI tester 200 can handle, that read data is allinputted from the I/O 19 b to a test circuit 15 a at a low speed, andthat the test circuit 15 a converts the bit width.

In the following descriptions it is assumed that the I/O 19 b includessixteen input terminals and that the width of data inputted to a testRAM 13 is 64 bits.

The test circuit 15 a includes a low-speed data input circuit fordividing read data into pieces of data and inputting each piece of datato the test RAM 13 at a low speed, a buffer for holding data outputtedfrom the low-speed data input circuit, and a low-speed data outputcircuit for dividing write data into pieces of data and outputting eachpiece of data to the I/O 19 b at a low speed.

FIG. 7 shows the low-speed data input circuit.

A low-speed data input circuit 151 includes sixty-four D flip-flops D00through D63.

When 16-bit read data b15 through b00, b31 through b16, b47 through b32,and b63 through 48 are inputted in this order from each input terminalof the I/O 19 b, each 16-bit read data is stored in the D flip-flops D00through D15, the D flip-flops D16 through D31, the D flip-flops D32through D47, and the D flip-flops D48 through D63 each time a low-speedclock is inputted. As a result, 64-bit low-speed read data b63 throughb00 is outputted. The low-speed read data b63 through b00 is held in a64-bit buffer (not shown).

FIG. 8 shows the low-speed data output circuit.

A low-speed data output circuit 152 includes sixty-four D flip-flops D00a through D63 a and sixteen selectors (two selectors 153 and 154 areshown in FIG. 8) to each of which output terminals of four D flip-flopsare connected. Output terminals of D flip-flops which output signalscorresponding to the same bit number of four pieces of data obtained bydividing 64-bit data into quarters are connected to each selector. Forexample, output terminals of the D flip-flops D63 a, D47 a, D31 a, andD15 a which output signals corresponding to the sixteenth bits areconnected to the selector 153.

A low-speed clock inputted from an input terminal 183 or an I/O clockoutputted from an oscillation circuit 12 may be used as a clock. Theselectors 153 and 154 are operated by a control signal inputted from aninput terminal 182.

64-bit low-speed write data c63 through c00 outputted from the test RAM13 is stored in the D flip-flops D63 a through D48 a, the D flip-flopsD47 a through D32 a, the D flip-flops D31 a through D16 a, and the Dflip-flops D15 a through D00 a. 16-bit low-speed write data c63 throughc48, 16-bit low-speed write data c47 through c32, 16-bit low-speed writedata c31 through c16, and 16-bit low-speed write data c15 through c00selected by the sixteen selectors are outputted to the LSI tester 200via output buffers included in the I/O 19 b.

FIGS. 9 and 10 show waveforms indicative of the operation of theintegrated circuit according to the fourth embodiment of the presentinvention.

In FIGS. 9 and 10, read data RN is divided into RNa, RNb, RNc, and RNdand is inputted. Write data WN is divided into WNa, WNb, WNc, and WNdand is outputted. The write data “Wxx” indicates that correspondingwrite data does not exist. Write enable is a kind of a control signaland indicates timing with which the test circuit 15 a writes read datato the test RAM 13. Read data is divided into four pieces of data (forexample, R00=R00 a, R00 b, R00 c, R00 d) each of which is made up ofsixteen bits and is inputted or outputted. Similarly, write data isdivided into four pieces of data each of which is made up of sixteenbits and is inputted or outputted.

The same effect that is obtained by the system according to the thirdembodiment of the present invention can be achieved by the systemaccording to the fourth embodiment of the present invention.

With the system according to the fourth embodiment of the presentinvention the I/O 19 b includes only the sixteen input terminals.However, 64-bit data can be supplied to the test RAM 13. That is to say,the system according to the fourth embodiment of the present inventionis effective especially in cases where the number of input terminals andoutput terminals which can be secured is smaller than the number of bitsincluded in data inputted at test time.

A system according to a fifth embodiment of the present invention willnow be described.

The differences between the systems according to the fourth and fifthembodiments of the present invention will mainly be described anddescriptions of the same matters will be omitted.

An integrated circuit 100 d according to the fifth embodiment of thepresent invention differs from the integrated circuit 100 c according tothe fourth embodiment of the present invention in that when a low-speeddata output circuit outputs low-speed write data to an externalterminal, the low-speed data output circuit compares low-speed writedata with 16-bit write data adjacent thereto and outputs a comparisonresult.

FIG. 11 is block diagram showing the system according to the fifthembodiment of the present invention.

The integrated circuit 100 d includes a test circuit 15 b including thelow-speed data output circuit for outputting a COMP signal (describedlater) and an output section 21 which functions as an interface foroutputting the COMP signal to an LSI tester 200.

FIG. 12 is a circuit diagram showing the low-speed data output circuitincluded in the integrated circuit according to the fifth embodiment ofthe present invention.

In a low-speed data output circuit 152 a, 64-bit low-speed write datac63 through c48, c47 through c32, c31 through c16, and c15 through c00outputted from a test RAM 13 is stored in D flip-flops D63 a through D48a, D flip-flops D47 a through D32 a, D flip-flops D31 a through D16 a,and D flip-flops D15 a through D00 a respectively. A comparator COMP3compares the write data c63 through c48 with the write data c47 throughc32, a comparator COMP2 compares the write data c47 through c32 with thewrite data c31 through c16, and a comparator COMP1 compares the writedata c31 through c16 with the write data c15 through c00. The COMPsignal indicative of comparison results is outputted to the LSI tester200 via an I/O 19 b. Hereinafter the COMP signal outputted will berepresented as “000” including outputs from the comparators COMP3,COMP2, and COMP1 in this order.

The (16 bits×4) low-speed write data outputted at a time from the testRAM 13 and the comparison results are referred to. If the write data c63through c48, the write data c47 through c32, the write data c31 throughc16, and the write data c15 through c00 are the same from the comparisonresults, each comparator outputs “1”. Accordingly, the test circuit 15 boutputs one piece of low-speed write data (16 bits) and the COMP signal“111”. As a result, outputting the write data once (one clock) enablesthe LSI tester 200 to decide the 64-bit data. If three of the write datac63 through c48, the write data c47 through c32, the write data c31through c16, and the write data c15 through c00 are the same, the testcircuit 15 b outputs two pieces of write data (16 bits×2) and one of theCOMP signals “110,” “101,” and “011”. For example, if the write data c63through c48, the write data c47 through c32, and the write data c31through c16 are the same, the test circuit 15 b outputs the COMP signal“110”. As a result, outputting the write data twice (two clocks) enablesthe LSI tester 200 to decide the 64-bit data. If two of the write datac63 through c48, the write data c47 through c32, the write data c31through c16, and the write data c15 through c00 are the same, the testcircuit 15 b outputs three pieces of write data (16 bits×3) and one ofthe COMP signals “100,” “010,” and “001”. For example, if the write datac63 through c48 and the write data c47 through c32 are the same, thetest circuit 15 b outputs the COMP signal “100”. As a result, outputtingthe write data three times (three clocks) enables the LSI tester 200 todecide the 64-bit data.

In FIG. 12, 16-bit write data and 16-bit write data adjacent thereto arecompared. However, there is no special limit to combination forcomparison. For example, the write data c63 through c48 and the writedata c31 through c16 may be compared, the write data c63 through c48 andthe write data c15 through c00 may be compared, or the write data c47through c32 and the write data c15 through c00 may be compared.

The same effect that is obtained by the system according to the fourthembodiment of the present invention can be achieved by the systemaccording to the fifth embodiment of the present invention. The fourpieces of 16-bit write data obtained by dividing the (16 bits×4) writedata read out from the test RAM 13 may be the same. In this case, 16-bitwrite data is outputted to en external terminal four times in the systemaccording to the fourth embodiment of the present invention. With thesystem according to the fifth embodiment of the present invention,however, 16-bit write data is outputted only once, so the number ofinput clocks can be reduced. As a result, test time can be reduced.

A system according to a sixth embodiment of the present invention willnow be described.

The differences between the systems according to the fifth and sixthembodiments of the present invention will mainly be described anddescriptions of the same matters will be omitted.

The structure of an integrated circuit according to the sixth embodimentof the present invention is the same as that of the integrated circuit100 d according to the fifth embodiment of the present invention. Theintegrated circuit according to the sixth embodiment of the presentinvention differs from the integrated circuit 100 d according to thefifth embodiment of the present invention in test signal pattern. To beconcrete, when a test circuit 15 b writes read data to a test RAM 13, anI/O clock is used. Similarly, when write data is read out to an LSItester 200, the I/O clock is used. When a piece of data is written issuccession, the piece of data and the number of the pieces of data aredesignated.

In this case, the piece of data and the number of the pieces of data aredesignated by a control signal. For example, it is assumed that when thetest circuit 15 b receives read data R01 a through R01 d, the testcircuit 15 b receives a control signal which indicates that read dataR01 through R03 are the same. Then the test circuit 15 b generates twopieces of read data each of which is the same as the read data R01 athrough R01 d. When the test circuit 15 b receives write enable, thetest circuit 15 b writes the three pieces of read data R01 a through R01d which are the same to the test RAM 13. The width of the write enableis proportional to the number of the written pieces of data which arethe same.

FIGS. 13 and 14 show waveforms indicative of the operation of theintegrated circuit according to the sixth embodiment of the presentinvention.

In FIGS. 13 and 14, read data R01 through R03 are the same, read dataR08 through R15 are the same, read data R17 through R21 are the same,and read data R24 through R31 are the same. In addition, write data c63through c48 included in write data W08 and W09 are the same and writedata c47 through c32 included in the write data W08 and W09 are thesame. Write data c63 through c48 included in write data W10 through W15are the same, write data c47 through c32 included in the write data W10through W15 are the same, write data c31 through c16 included in thewrite data W10 through W15 are the same, and write data c15 through c00included in the write data W10 through W15 are the same. The width ofwrite enable is proportional to the number of written pieces of datawhich are the same. “COMP” indicates a COMP signal outputted to anoutput section 21. As stated above, the COMP signal “001” indicates thatwrite data WNc and WNd are the same and the COMP signal “111” indicatesthat write data WNa, WNb, WNc, and WNd are the same.

Descriptions of the same matters that are described regarding thewaveforms indicative of the operation of the integrated circuit 100according to the first embodiment of the present invention will beomitted.

In the integrated circuit according to the sixth embodiment of thepresent invention, the test circuit 15 b first reads read data at a lowspeed.

When the test circuit 15 b receives write enable (time A1), the testcircuit 15 b writes the read data to the test RAM 13 at a low speed. Asa result, the amount of read data stored in the test RAM 13 increases byone.

When the test circuit 15 b then receives write enable (time B1), thetest circuit 15 b writes the read data R01 through R03 which are thesame to the test RAM 13 at a low speed. As a result, the amount of readdata stored in the test RAM 13 increases by three.

When an external memory control circuit 11 outputs a read command to atest circuit 14 (time C1), the test circuit 14 reads out the read datafrom the test RAM 13 to the external memory control circuit 11 at a highspeed.

When the external memory control circuit 11 outputs the read command tothe test circuit 14 (time C1), the test circuit 14 writes write datafrom the external memory control circuit 11 to the test RAM 13 at a highspeed.

The operation is performed in this way. Instructions to output writedata from the test circuit 15 b are given by a control signal. Writedata W08 a, W08 b, and W08 c are written to the test RAM 13. When acomparator outputs the COMP signal “001,” the COMP signal “001” isoutputted to the output section 21 and the write data W08 a, W08 b, andW08 c are outputted to an I/O 19 b (time D1). When write data W10 a(WNa) is written to the test RAM 13 (not shown), the test RAM 13 outputsthe COMP signal “111” to the output section 21 and outputs the writedata W10 a to the I/O 19 b.

The same effect that is obtained by the system according to the fifthembodiment of the present invention can be achieved by the systemaccording to the sixth embodiment of the present invention.

With the system according to the sixth embodiment of the presentinvention, writing from the test circuit 15 b to the test RAM 13 isperformed at a high speed and the amount of data outputted at a lowspeed after the reading by the test circuit 14 is reduced. Therefore,test time can be reduced compared with the system according to the fifthembodiment of the present invention. By using data in which the samepiece of data appears in succession in read data or write dataespecially in the case of, for example, an image, time taken to test theencoding or decoding of a dynamic image can be reduced significantly.

A system according to a seventh embodiment of the present invention willnow be described.

The differences between the systems according to the fifth and seventhembodiments of the present invention will mainly be described anddescriptions of the same matters will be omitted.

FIG. 15 is block diagram showing the system according to the seventhembodiment of the present invention. An arrow in FIG. 15 indicates thedirection of a signal.

An integrated circuit 100 e according to the seventh embodiment of thepresent invention includes two external memory control circuits 11 a and11 b, a test RAM 13 a for accepting write data sent from the externalmemory control circuit 11 a, a test RAM 13 b for accepting read datasent to the external memory control circuit 11 a, a test RAM 13 c foraccepting write data sent from the external memory control circuit 11 b,a test RAM 13 d for accepting read data sent to the external memorycontrol circuit 11 b, test circuits 14 a and 14 b which function thesame as the test circuit 14, and a test circuit 15 c which functions thesame as the test circuit 15 b and which exchanges data with each testRAM.

An LSI tester 200 inputs read data and write data to the external memorycontrol circuits 11 a and 11 b. The read data and the write data arecommon to the external memory control circuits 11 a and 11 b. Each ofthe test circuits 14 a and 14 b receives the type of read/write andtiming in place of a memory command.

A low-speed data input circuit and a low-speed data output circuitincluded in the test circuit 15 c of the integrated circuit 100 eaccording to the seventh embodiment of the present invention will bedescribed.

FIG. 16 shows a low-speed data input circuit included in the integratedcircuit according to the seventh embodiment of the present invention.

In this example, the width of data handled by the external memorycontrol circuits 11 a and 11 b is 64 bits and a low-speed data inputcircuit 151 a has sixteen terminals used for low-speed data input.

The LSI tester 200 inputs read data to the low-speed data input circuit151 a in the order of b63 through b48, b47 through b32, b31 through b16,and b15 through b00. There are many cases where the same piece of dataappears in succession in, for example, image data. Accordingly,selectors are located at stages before D flip-flops D0 b through D15 b,D flip-flops D16 b through D31 b, and D flip-flops D32 b through D47 bso that the read data b63 through b48, b47 through b32, b31 through b16,and b15 through b00 which are separated every sixteen bits and which arethe same can be inputted by one clock. However, the read data b63through b48 can be inputted from the terminals, so selectors are notlocated at a stage before D flip-flops D48 b through D63 b. “0” isinputted to each selector with a case where data stored in memoriescleared to zero is read taken into consideration.

FIG. 17 shows a low-speed data output circuit included in the integratedcircuit according to the seventh embodiment of the present invention.

A low-speed data output circuit 152 a includes buffers located at twostages (in two columns), so input of write data from the test RAMs 13 aand 13 c and output of write data to an I/O 19 can be performed at thesame time.

FIG. 18 shows waveforms indicative of the operation of the integratedcircuit according to the seventh embodiment of the present invention.

In FIG. 18, “A-side WAIT” indicates WAIT inputted to the external memorycontrol circuit 11 a, “A-side read” indicates that the test RAM 13 breads out data to the external memory control circuit 11 a, “A-sidewrite” indicates that the external memory control circuit 11 a writesdata to the test RAM 13 a, “B-side WAIT” indicates WAIT inputted to theexternal memory control circuit 11 b, “B-side read” indicates that thetest RAM 13 d reads out data to the external memory control circuit 11a, “B-side write” indicates that the external memory control circuit 11a writes data to the test RAM 13 c, “write enable A” indicates a writepermission signal by which the LSI tester 200 can write read data A tothe test circuit 15 c, the “read data A” indicates read data to bestored in the test RAM 13 a, “amount A of read data” indicates theamount of read data stored in the test RAM 13 a, “write enable B”indicates a write permission signal by which the LSI tester 200 canwrite the read data B to the test circuit 15 c, “read data B” indicatesread data to be stored in the test RAM 13 c, “amount B of read data”indicates the amount of read data stored in the test RAM 13 c, “amount Aof write data” indicates the amount of write data stored in the test RAM13 b, and “amount B of write data” indicates the amount of write datastored in the test RAM 13 d.

It is assumed that read data sent to the external memory control circuit11 a is RAn={RAnd, RAnc, RAnb, RAna}, that read data sent to theexternal memory control circuit 11 b is RBn={RBnd, RBnc, RBnb, RBna},that write data sent to the external memory control circuit 11 a isWAn={WAnd, WAnc, WAnb, WAna}, and that write data sent to the externalmemory control circuit 11 b is WBn={WBnd, WBnc, WBnb, WBna}.

In FIG. 18, the width of write enable is proportional to the number ofwritten pieces of data which are the same. For example, RA1 is writtenthree times and RB4 is written four times.

The operation of the integrated circuit 100 e according to the seventhembodiment of the present invention is approximately the same as that ofthe integrated circuit 100 d according to the fifth (sixth) embodimentof the present invention, so descriptions of the operation of theintegrated circuit 100 e according to the seventh embodiment of thepresent invention will be omitted.

The same effect that is obtained by the system according to the fifthembodiment of the present invention can be achieved by the systemaccording to the seventh embodiment of the present invention.

A system according to an eighth embodiment of the present invention willnow be described.

The differences between the systems according to the seventh and eighthembodiments of the present invention will mainly be described anddescriptions of the same matters will be omitted.

FIG. 19 is block diagram showing the system according to the eighthembodiment of the present invention.

An integrated circuit 100 f according to the eighth embodiment of thepresent invention can be applied to a case where a double data ratesynchronous dynamic (DDRSD) RAM is used as an external memory.

The integrated circuit 100 f includes a data input circuit 22 a locatedbetween an input buffer included in an I/O 16 a and a selector 173 a, adata input circuit 22 b located between an input buffer included in anI/O 16 b and a selector 173 b, a data output circuit 23 a locatedbetween an external memory control circuit 11 a and an output bufferincluded in the I/O 16 a, and a data output circuit 23 b located betweenan external memory control circuit 11 b and an output buffer included inthe I/O 16 b. An I/O clock and a control signal (not shown) are inputtedto each of the data input circuits 22 a and 22 b and the data outputcircuits 23 a and 23 b.

FIG. 20 shows a data input circuit included in the integrated circuitaccording to the eighth embodiment of the present invention. The datainput circuit 22 a is shown in FIG. 20.

The data input circuit 22 a includes flip-flop groups FF1 through FF3each including a total of 2n D flip-flops. That is to say, eachflip-flop group is made up of n D flip-flops D0 e through D(n-1)e and nD flip-flops D(n)e through D(2(n-1))e.

The data input circuit 22 a transfers data which synchronizes with therise of an I/O clock and data which synchronizes with the rise of aninverted I/O clock.

First, read data inputted from an LSI tester 200 via the I/O 16 a islatched by the flip-flop group FF1. The D flip-flops D0 e throughD(n-1)e latch the read data at the rise of the I/O clock and the Dflip-flops D(n)e through D(2(n-1))e latch the read data at the rise ofthe inverted I/O clock.

The flip-flop group FF2 latches output from the flip-flop group FF1 atthe next rise of the I/O clock.

The flip-flop group FF3 then latches output from the flip-flop group FF2on the basis of an internal clock and outputs the read data to theselector 173 a.

FIG. 21 shows a data output circuit included in the integrated circuitaccording to the eighth embodiment of the present invention. The dataoutput circuit 23 a is shown in FIG. 21.

The data output circuit 23 a includes a D flip-flop group FF4 includinga total of 2n D flip-flops and selectors 221 a and 222 a located on theoutput side of the D flip-flop group FF4. The D flip-flop group FF4includes n D flip-flops D0 f through D(n-1)f and n D flip-flops D(n)fthrough D(2(n-1))f.

Write data inputted from the external memory control circuit 11 a islatched by the D flip-flop group FF4 at the rise of a clock. Write dataselected by a selection signal is outputted from the selectors 221 a and222 a to the I/O 16 a at the next rise of the clock.

The same effect that is obtained by the system according to the seventhembodiment of the present invention can be achieved by the systemaccording to the eighth embodiment of the present invention. As statedabove, the system according to the eighth embodiment of the presentinvention can also be applied to a case where a DDRSDRAM is used as anexternal memory.

A system according to a ninth embodiment of the present invention willnow be described.

The differences between the systems according to the seventh and ninthembodiments of the present invention will mainly be described anddescriptions of the same matters will be omitted.

Unlike the integrated circuit according to the seventh embodiment of thepresent invention, an integrated circuit according to the ninthembodiment of the present invention can also cope with a case wherelow-speed input and low-speed output of data cannot be performed at thesame time because of the number of terminals which can be used forcontrolling low-speed data input-output being small. The structure ofthe integrated circuit according to the ninth embodiment of the presentinvention is the same as that of the integrated circuit 100 e accordingto the seventh embodiment of the present invention.

FIG. 22 shows waveforms indicative of the operation of the integratedcircuit according to the ninth embodiment of the present invention.

In FIG. 22, “control signal” indicates a control signal inputted to atest circuit 15 c. The meanings of the control signal are as follows.

IN1: Read data is inputted at a low speed to a test RAM 13 a or 13 b inorder sixteen bits at a time.

IN0: Write data c63 through c48 is inputted from an I/O 19 b at a lowspeed and “0” is inputted to each selector in a low-speed data inputcircuit 151 a.

WA1: One word is written to the test RAM 13 a.

WA3: Three words are written to the test RAM 13 a.

IN1RA: Read data is inputted at a low speed in order sixteen bits at atime and one word is read from the test RAM 13 b.

OUT1: A low-speed data output circuit outputs write data c47 through C32of low-speed write data read from the test RAM 13 a.

OUT2: The low-speed data output circuit outputs write data c15 throughC00 of low-speed write data read from the test RAM 13 a.

OUT3: The low-speed data output circuit outputs write data c31 throughC16 of low-speed write data read from the test RAM 13 a.

The low-speed data output circuit always outputs write data c63 throughC48 during a period other than OUT1 through OUT3.

The operation of the integrated circuit according to the ninthembodiment of the present invention will now be described. However,descriptions of the operation of the integrated circuit according to theninth embodiment of the present invention which is the same as that ofthe integrated circuit 100 d according to the fifth (sixth) embodimentof the present invention will be omitted.

The control signal IN1 is inputted first and read data RA0 a through RA0d is inputted at a low speed to the test RAM 13 a in order sixteen bitsat a time (time A2).

The control signal WA1 is then inputted and read data RA0 for one word,that is to say, the read data RA0 a through RA0 d is written to the testRAM 13 a at a low speed (time B2).

The control signal IN1 is then inputted and read data RA1 a through RA1d is inputted at a low speed to the test RAM 13 a in order sixteen bitsat a time (time C2).

The control signal WA3 is then inputted and read data RA1 for threewords, that is to say, the read data RA1 a through RA1 d for three wordsis written to the test RAM 13 a at a low speed (time D2).

The control signal WB1 is then inputted and read data RB0 for one word,that is to say, read data RB0 a through RB0 d is written to a test RAM13 c at a low speed (time E2).

After that, processes are performed in order. The control signal IN1RAis inputted (time F2). As a result, read data is inputted at a low speedin order sixteen bits at a time and one word is read from the test RAM13 b.

The control signal OUT1 is then inputted (time G2) and write data b47through b32 is outputted from the low-speed data output circuit 152 a.

The control signal IN0 is then inputted (time H2). As a result, “0” isinputted to each selector in the low-speed data input circuit 151 a andwrite data b63 through b48 is inputted from an I/O 16 a at a low speed.

After that, operation is performed in the same way.

The same effect that is obtained by the system according to the seventhembodiment of the present invention can be achieved by the systemaccording to the ninth embodiment of the present invention.

The system according to the ninth embodiment of the present inventioncan also cope with a case where low-speed input and low-speed output ofdata cannot be performed at the same time because of the number ofterminals which can be used for controlling low-speed data input-outputbeing small by changing the pattern of inputting control signals.

A system according to a tenth embodiment of the present invention willnow be described.

The differences between the systems according to the fifth and tenthembodiments of the present invention will mainly be described anddescriptions of the same matters will be omitted.

An integrated circuit 100 g according to the tenth embodiment of thepresent invention differs from the integrated circuit 100 d according tothe fifth embodiment of the present invention in that an external memorycontrol circuit 11 is in a wait state (by WAIT) by default.

FIG. 23 is block diagram showing a system according to the tenthembodiment of the present invention.

The integrated circuit 100 g according to the tenth embodiment of thepresent invention includes an adjustment circuit 111 for managing aplurality of requests from an internal circuit 10 to access a test RAM13 (REQ_A and REQ_B in this example).

An LSI tester 200 sets the external memory control circuit 11 to a waitstate (by WAIT) via a test circuit 15 b by default.

FIG. 24 shows waveforms indicative of the operation of the integratedcircuit according to the tenth embodiment of the present invention. InFIG. 24, “REQ_A (read)” and “REQ_B (read)” indicate read access requestsfrom the internal circuit 10, “begin reading,” “terminate reading,” and“transfer data at read time” indicate operation performed by theexternal memory control circuit 11, “REQ_A (write)” and “REQ_B (write)”indicate read access requests from the internal circuit 10, and “beginwriting,” “terminate writing,” and “transfer data at write time”indicate operation performed by the external memory control circuit 11.

In FIG. 24, when the external memory control circuit 11 reads read data,necessary data is written to a write data area of the test RAM 13. Whenthe external memory control circuit 11 writes write data, the wait stateof the external memory control circuit 11 is released and the externalmemory control circuit 11 is set to a wait state after one low-speedclock pulse. This is based on the assumption that there is sufficientspace in the write data area of the test RAM 13. An external memoryaccess may occur twice during the one low-speed clock pulse during whichthe wait state of the external memory control circuit 11 is released.

The same effect that is obtained by the system according to the fifthembodiment of the present invention can be achieved by the systemaccording to the tenth embodiment of the present invention.

With the system according to the tenth embodiment of the presentinvention, the next access begins before the preceding memory accessterminates. This increases efficiency in external memory access.Moreover, depending on the structure of the external memory controlcircuit 11 or the type of an external memory, it is possible to overlapmemory access operations. For example, if the external memory is anSDRAM and different banks are accessed, a bank can be made active forthe next memory access during read/write.

A system according to an eleventh embodiment of the present inventionwill now be described.

The differences between the systems according to the tenth and eleventhembodiments of the present invention will mainly be described anddescriptions of the same matters will be omitted.

With the integrated circuit 100 g according to the tenth embodiment ofthe present invention the external memory control circuit 11 is alwaysin a wait state (by WAIT) so that external memory accesses will notoverlap. The wait state of the external memory control circuit 11 isreleased only during one low-speed clock pulse. However, if the speed ofan internal clock is high, two memory accesses may occur. An integratedcircuit according to the eleventh embodiment of the present inventiondiffers from the integrated circuit 100 g according to the tenthembodiment of the present invention in that the occurrence of two memoryaccesses is prevented.

FIG. 25 is block diagram showing the system according to the eleventhembodiment of the present invention.

To prevent the occurrence of two memory accesses, an integrated circuit100 h according to the eleventh embodiment of the present inventionincludes an edge detection circuit 24 for detecting the trailing edge ofa WAIT signal.

When the edge detection circuit 24 detects the trailing edge of a WAITsignal, the edge detection circuit 24 outputs an edge pulse forreleasing the wait state of an external memory control circuit 11 duringone I/O clock pulse to the external memory control circuit 11. If aclock for an adjustment circuit 111 included in the external memorycontrol circuit 11 differs from an I/O clock, then the wait state of theexternal memory control circuit 11 is released during one pulse of theclock for the adjustment circuit 111.

FIG. 26 shows waveforms indicative of the operation of the integratedcircuit according to the eleventh embodiment of the present invention.

For one edge pulse outputted from the edge detection circuit 24, thewait state of the external memory control circuit 11 is released duringone clock pulse. Accordingly, an external memory access occurs onlyonce. As a result, the timing of the external memory access can becontrolled reliably by a control signal inputted to a test circuit 15 b.This is effective especially in the case where the amount of dataincluded in the longest burst of an external memory access isapproximately the same as the capacity of a test RAM 13. It is assumedthat the preceding write (or read) and longest-burst write (or read)overlap. With the integrated circuit 100 g according to the tenthembodiment of the present invention the test RAM 13 overflows with writedata (or the capacity of the test RAM 13 runs short). With theintegrated circuit 100 h according to the eleventh embodiment of thepresent invention, however, the test RAM 13 does not overflow with data(or the capacity of the test RAM 13 does not run short). In addition, atest circuit or a test signal generation simulation can be debuggedeasily.

In the present invention the command interpretation circuit interprets acommand issued by the control circuit and a data transfer is performedbetween the test storage section and the circuit only at the time ofinputting or outputting necessary data. As a result, test time can bereduced significantly. In addition, there is no need to read uselessdata. Therefore, the size of the test storage section can be reduced andthe size of the integrated circuit can be reduced.

The foregoing is considered as illustrative only of the principles ofthe present invention. Further, since numerous modifications and changeswill readily occur to those skilled in the art, it is not desired tolimit the invention to the exact construction and applications shown anddescribed, and accordingly, all suitable modifications and equivalentsmay be regarded as falling within the scope of the invention in theappended claims and their equivalents.

1. An integrated circuit capable of verifying an operation speed of acircuit, the integrated circuit comprising: an internal circuit to betested; a control circuit, located between the internal circuit and anexternal device, for inputting read data to the internal circuit fromthe external device by the use of a read command and for outputtingwrite data outputted from the internal circuit to the external device bythe use of a write command; a test storage section including a read datastorage section for storing the read data inputted at a low speed and awrite data storage section for storing the write data outputted from thecontrol circuit; a command interpretation circuit for interpreting theread command and the write command issued by the control circuit, forsupplying, at the time of determining that the read data must beinputted to the control circuit, the read data from the test storagesection to the control circuit at a high speed, and for supplying, atthe time of determining that the write data is outputted from thecontrol circuit, the write data outputted from the control circuit tothe test storage section at a high speed; an input circuit for inputtingthe read data inputted from the external device to the test storagesection at a low speed; and an output circuit for outputting the writedata supplied to the test storage section to the external device at alow speed.
 2. The integrated circuit according to claim 1, wherein:input of the read data and output of the write data are performedbetween the command interpretation circuit and the test storage section;the input circuit inputs the read data to the test storage section; andthe output circuit outputs the write data to the external device.
 3. Theintegrated circuit according to claim 1, wherein the input circuit isintegrated with the output circuit.
 4. The integrated circuit accordingto claim 1, wherein the external device inputs a low-speed clock foroperation to the input circuit and the output circuit and inputs a clockfor operation having a speed higher than a speed of the low-speed clockto the command interpretation circuit.
 5. The integrated circuitaccording to claim 1, further comprising: a data input-output sectionfor performing direct input-output of data between the control circuitand an outside; and a low-speed data input-output section for performinginput-output of data between the control circuit and the outside via thetest storage section, wherein the data input-output section and thelow-speed data input-output section are separately provided.
 6. Theintegrated circuit according to claim 5, further comprising a conversioncircuit for converting bit width of data inputted to and outputted fromthe low-speed data input-output section and bit width of data inputtedto and outputted from the test storage section.
 7. The integratedcircuit according to claim 6, wherein the conversion circuit is locatedbetween the test storage section and the external device, includes acomparison circuit for determining by comparison whether plural piecesof write data outputted from the test storage section are the same, andoutputs, in the case of the plural pieces of write data being the same,one of the plural pieces of write data and a result obtained by thecomparison by the comparison circuit to the low-speed data input-outputsection.
 8. The integrated circuit according to claim 1, wherein: theexternal device outputs WAIT to the control circuit by default; and theexternal device releases the WAIT when all the read data is not storedin the test storage section or when there is not sufficient space in thetest storage section to store the write data.
 9. The integrated circuitaccording to claim 8, further comprising a detection circuit fordetecting an edge of the WAIT and for generating an edge pulse which isequal to one pulse of a clock of the control circuit, wherein thecontrol circuit releases the WAIT by inputting the edge pulse thereto.10. The integrated circuit according to claim 1, wherein the externaldevice is a tester for verifying an operation speed of the integratedcircuit.
 11. The integrated circuit according to claim 1, furthercomprising a selector for switching between the read data directlyinputted from the external device to the control circuit and the readdata inputted via the test storage section.
 12. The integrated circuitaccording to claim 1, further comprising a selector for switchingbetween the write data directly outputted from the control circuit tothe external device and the write data outputted via the test storagesection.
 13. The integrated circuit according to claim 1, wherein theexternal device operates the input circuit so as to input the read datato the test storage section at a low speed according to timing at whichthe command interpretation circuit outputs the read command.
 14. Theintegrated circuit according to claim 1, wherein the external deviceoperates the output circuit so as to output the write data from the teststorage section at a low speed according to timing at which the commandinterpretation circuit outputs the write command.